📝 Publication

PALUTE: Processing-In-Memory Acceleration via Lookup Table for Edge LLM Inference
Runyang Tian, Yanru Chen, Weihong Xu, Tajana Rosing.

• Proposed a LUT-based processing-in-memory accelerator using monolithic 3D DRAM for efficient low-bit edge LLM inference.
• Developed an in-DRAM LUT query mechanism and near-memory LUT generator to reduce dequantization, GEMM, nonlinear-operation, and data-movement overheads.
• Achieved 1,264 TPS at 0.16 W, improving energy efficiency by 12.8× over CHIME and 1.6× over FIGLUT, with 2.0× higher area efficiency than PIMPAL under W4A4 inference.

CHIME: Chiplet-based Heterogeneous Near-Memory Acceleration for Edge Multimodal LLM Inference
Yanru Chen*, Runyang Tian*, Yue Pan, Zheyu Li, Weihong Xu, Tajana Rosing.

• Proposed a heterogeneous architecture that integrates M3D DRAM (low-latency, high-endurance) and M3D RRAM (high-density, low-refresh-energy) chiplets.
• Proposed a mapping and scheduling framework for heterogeneous near-memory kernels to fully use the complementary benefits of both memories.
• Improved the energy effciency 246x and speedup 53x compared with Jetson Orin NX. 69.2x higher throughput than the SOTA.