Welcome to my homepage! I am Runyang Tian, currently a PhD student in Computer Engineering at the University of California Santa Barbara, advised by Professor Peng Li. I received my Master’s degree in Electrical Engineering at the University of California San Diego, advised by Professor Tajana Šimunić Rosing. My research interest includes Memory-Centric Computing, Brain-Inspired Computing and AI for EDA.

🔥 News

  • 2026.05: 🎉 One paper is accepted by ISLPED 2026
  • 2026.02: 🎉 One paper is accepted by DAC 2026
  • 2025.11: 🎉 Two papers are accepted by DATE 2026

📝 Publication

ISLPED 2026
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PALUTE: Processing-In-Memory Acceleration via Lookup Table for Edge LLM Inference
Runyang Tian, Yanru Chen, Weihong Xu, Tajana Rosing.

  • Proposed a LUT-based processing-in-memory accelerator using monolithic 3D DRAM for efficient low-bit edge LLM inference.
  • Developed an in-DRAM LUT query mechanism and near-memory LUT generator to reduce dequantization, GEMM, nonlinear-operation, and data-movement overheads.
  • Achieved 1,264 TPS at 0.16 W, improving energy efficiency by 12.8× over CHIME and 1.6× over FIGLUT, with 2.0× higher area efficiency than PIMPAL under W4A4 inference.
DATE 2026
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CHIME: Chiplet-based Heterogeneous Near-Memory Acceleration for Edge Multimodal LLM Inference
Yanru Chen*, Runyang Tian*, Yue Pan, Zheyu Li, Weihong Xu, Tajana Rosing.

  • Proposed a heterogeneous architecture that integrates M3D DRAM (low-latency, high-endurance) and M3D RRAM (high-density, low-refresh-energy) chiplets.
  • Proposed a mapping and scheduling framework for heterogeneous near-memory kernels to fully use the complementary benefits of both memories.
  • Improved the energy effciency 246x and speedup 53x compared with Jetson Orin NX. 69.2x higher throughput than the SOTA.

🏫 Education

  • 2026.09 - Now, Ph.D. Computer Engineering, University of California Santa Barbara
  • 2024.09 - 2026.06, M.S. Electrical Engineering, University of California San Diego
  • 2020.09 - 2024.06, B.E. Microelectronic, Xi’an Jiaotong University

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